HDLBits 系列（32）Sequence recognition（序列检测）
目录
原题复现
Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the data stream from accidentally containing "flags", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s.
Create a finite state machine to recognize these three sequences:
- 0111110: Signal a bit needs to be discarded (disc).
- 01111110: Flag the beginning/end of a frame (flag).
- 01111111...: Error (7 or more 1s) (err).
When the FSM is reset, it should be in a state that behaves as though the previous input were 0.
Here are some example sequences that illustrate the desired operation.
审题
根据题目来看，这是一个序列识别的一个问题，如果识别到序列有连续5个1（即1111_10），则disc有效；
如果有连续6个1（即1111_110），则flag有效；
如果有连续7个1或者更多的1，则err有效。
状态转移图
就是这样一个问题，我们根据上述波形图来画出状态转移图：
我的设计
根据状态转移图，很容易得到设计：
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module top_module(
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input clk,
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input reset, // Synchronous reset
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input in,
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output disc,
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output flag,
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output err);
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localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, DISC = 7, FLAG = 8, ERR = 9;
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reg [3:0] state, next_state;
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always@(*) begin
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case(state)
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S0: begin
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if(in) next_state = S1;
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else next_state = S0;
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end
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S1: begin
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if(in) next_state = S2;
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else next_state = S0;
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end
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S2: begin
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if(in) next_state = S3;
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else next_state = S0;
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end
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S3: begin
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if(in) next_state = S4;
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else next_state = S0;
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end
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S4: begin
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if(in) next_state = S5;
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else next_state = S0;
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end
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S5: begin
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if(in) next_state = S6;
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else next_state = DISC;
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end
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S6: begin
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if(in) next_state = ERR;
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else next_state = FLAG;
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end
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DISC: begin
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if(in) next_state = S1;
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else next_state = S0;
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end
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FLAG: begin
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if(in) next_state = S1;
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else next_state = S0;
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end
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ERR: begin
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if(in) next_state = ERR;
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else next_state = S0;
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end
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default: begin
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next_state = S0;
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end
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endcase
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end
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always@(posedge clk)begin
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if(reset) state <= S0;
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else state <= next_state;
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end
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assign disc = (state == DISC)?1:0;
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assign flag = (state == FLAG)?1:0;
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assign err = (state == ERR)?1:0;
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-
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endmodule
测试成功！
这是序列检测的一个典型做法，校招可没少做这种题目，只是好像都还要比这个简单。
文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。
原文链接：reborn.blog.csdn.net/article/details/103446185
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